Schematic and info HERE
*Edit 200726*
Now verified.
*Edit2 200802*
Uploaded the the verified layout.
Thanks to brianhujung for pointing it out.
*Edit 200726*
Now verified.
*Edit2 200802*
Uploaded the the verified layout.
Thanks to brianhujung for pointing it out.
This comment has been removed by the author.
ReplyDeleteHi, thanks for this vero layout.. I have several questions if you don't mind :
ReplyDelete1. 1k resistor bottom left connected to Source pin of the 1st Jfet. Bajaman schematic value is 10k while yours is 1k. Is it a mods?
2. There's 1k resistor connected between IC2 pin 2 to 10nf (coupling cap after IC1 pin 1) which I can't find on the schematic.. can you enlighten me?
3. 22nF connected at IC1 pin 3 is connected to ground instead of Vbias..
I don't have much experience which vero so even if it's verified, I still double checking the layout. I'm using Bajaman schematic rev 2 jan 2020..
Thanks again for the layout,
Cheers..
Thanks for pointing these issues out. It turns out that I forgot to upload the latest version of the layout. Q1 source reistor is 10k indeed. The 1k resistor connecting to IC2 should be left out altohether. And the 22nF cap is connected to vbias as you mentioned. Uploaded the layout I verified which includes all the changes.
DeleteThanks again for pointing it out!